Faraday Adopts Cadence Encounter Platform for Structured ASIC Design
TAIPEI, China—(BUSINESS WIRE)—Dec. 10, 2003—
Cadence Design Systems, Inc. (NYSE:CDN) and Faraday
Technology Corporation (TAIEX:3035) today announced that Faraday has
successfully developed a design implementation flow for its Metal
Programmable Cell Array (MPCA) structured ASIC technology, using the
Cadence(R) Encounter(TM) digital IC design platform. Cadence is the
first EDA vendor to enable Faraday to conduct actual chip
implementation methodology with its structured ASIC paradigm.
Structured ASIC Flow with the Encounter(TM) System
Faraday's structured ASIC implementation flow was based on
Cadence's leading-edge continuous convergence methodology provided by
the Cadence Encounter platform. The flow was successfully validated
with an actual test chip tape-out in May 2003. The major benefit of
the flow is that it helps Faraday engineers drive its customer design
netlist from a structured ASIC floorplan specification to a physical
design, with fast and guaranteed timing and signal integrity (SI)
closure. The necessary capabilities include silicon virtual
prototyping, floorplanning, placement and routing, clock tree
synthesis, physical timing optimization, RC extraction, SI crosstalk
closure, and physical ECO.
"Our customers can enjoy accelerated development cycles and lower
derivation costs by using the winning combination of Faraday's MPCA
technology, mass production proven intellectual property (IP)
portfolios, and state-of-the-art ASIC services," said Hsin Wang,
senior technical director of Faraday "Encounter greatly helps us
fine-tune designs at an early stage and drives fast design closure on
timing, power, and signal integrity," he added.
"We are absolutely delighted to have been selected by Faraday to
join them in the utilization of this pioneering structured ASIC
technology," said Wei-Jin Dai, vice president of research and
development at Cadence. "This successful cooperation highlights our
commitment to customer success and further validates the significance
of our Encounter platform."
About Faraday Technology Corporation
Faraday Technology Corporation provides leading ASIC/SoC design
services and production-proven IPs to customers ranging from system
houses and IDMs to IC design houses. The company's broad portfolio of
key IPs includes leading products such as RISC CPUs, 16/20/24-bit
DSPs, USB 2.0, gigabit Ethernet, and Serial-ATA. Faraday's ASIC design
services and IPs are widely used in PC peripherals, communication, and
digital consumer products. With more than 480 employees and 2002
revenue of 96.2 million USD, Faraday is the largest fabless ASIC
design service company in all Asia-Pacific. Headquartered in Hsinchu
Taiwan, Faraday offers service and support branch offices around the
world, including the U.S., Japan, Europe, and China. For more
information on Faraday, please visit http://www.faraday.com.tw
About Cadence
Cadence is the largest supplier of electronic design technologies,
methodology services, and design services. Cadence solutions are used
to accelerate and manage the design of semiconductors, computer
systems, networking and telecommunications equipment, consumer
electronics, and a variety of other electronics based products. With
approximately 5,000 employees and 2002 revenues of approximately $1.3
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and traded on the New York Stock Exchange under the symbol
CDN. More information about the company, its products and services is
available at www.cadence.com.
Cadence and the Cadence logo are registered trademarks of Cadence
Design Systems, Inc. and Encounter is a trademark of Cadence. All
other trademarks are the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Al Feng, +886-35663804
alfeng@cadence.com
or
Faraday Technology Corporation
Selina Ko, +886-35787888
selina@faraday.com.tw
